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Altera_Forum's avatar
Altera_Forum
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13 years ago

Logic family for REFCLK

For a new design we need to provide a 150MHz REFCLK to a set of Cyclone V transceivers. The oscillator output will only drive the REFCLK inputs. My question is which logic family I should use for the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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We have successfully driven REFCLK pins to PLLs, generated our frequency for user logic AND Serdes' refclk ports in arria v. I suspect you can do the same for CV. We used lvds or lvpecl. AC coupling's the most important part

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Are you able to use the REFCLK pin if you do not instantiate a SerDes block? I haven't tried this with any of the V series devices, but its not possible with the IV series. The work-around is to create an ALTGX+ALTGX_RECONFIG component, and then essentially not use it (reset it).

Cheers,

Dave