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DinhLe's avatar
DinhLe
Icon for New Contributor rankNew Contributor
1 year ago

local_cal_fail is assert when running DDR3 SDRAM Test by Nios II example on Sockit Rev D board

Hi, I have a problem relate to DDR3 interface when running DDR3 SDRAM Test by Nios II, local_init_done is asserted. I tried to debug and search information but there is no more information. Can you ...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Can you generate the example design in latest Quartus release? because the Quartus 13.1 is already EOL.


The previous snapshot that you have shared when using the EMIF Debug Toolkit has shown the device used is 5CESBA6.

Maybe you can double check the device used in the design and make sure it's matching to the FPGA device on the board.

I highly recommend using latest Quartus version to debug the DDR3 issue as the issue might be with the tools in Quartus 13.1.


Another suggestion that you can try is to lower the JTAG frequency to 6MHz in the Programmer before downloading the sof file into the FPGA device.

You also can check the timing report and make sure the design doesn't have timing violation.



Regards,

Adzim