I have a design which needs data preloaded into one or more of NVRAM and/or SRAM and/or SDRAM on a DE1. I am using Quartus II Web Edition 11.1 sp1. I am not using Qsys, SOPC or NIOS, as the design is very simple, doesn't use NIOS etc. I am running on Linux. The amount of data I want to preload is too much to pre-initialise onboard in the FGPA design itself (ie: in M4K or LE constructed memory). Whats the simplest way I can do this? (I am a beginner, and at the moment am getting to grips with Quartus, I'm rather hoping I don't have to learn Qsys, SOPC or NIOS to do this). The Windows DE1 Control Panel doesn't seem to be available for Linux. Thanks {{{ Andy

Hi Andy, Since you are a beginner, it would be useful for you to describe what you are trying to do, and what needs to be initialized. That way others can offer alternative solutions. For example, it looks like the DE1 has Flash and an SD card. Flash is probably the easiest to use, since your logic in the FPGA can read it after power-on. However, perhaps the SD card would be more useful, since you can plug it into your PC and write data to it there. But then again, perhaps you don't really need either of these. What you may really need is a connection between your PC and the DE1 so that you can transfer data to on-board memory, and then 'enable' your FPGA logic. Cheers, Dave

Dave, I am (slowly) recreating an 8-bit computer from the late 80s. As I can't post links yet, Google for "nyangau" and "memotech", and follow the link to REMEMOTECH. I need quite a lot of ROM data persisted somewhere, so I am thinking Flash. I need much more RAM than will fit on-chip, so I am thinking SRAM. I am also thinking of using SDRAM as "Silicon disc". As the flash has 70ns access time, I may need to add wait states to the CPU, and perhaps arrange that the bootstrap code copy from flash to SRAM, make it read-only, so as to speed up future accesses. In the interim before working out the above paragraph, I was planning to pre-load SRAM directly. Being able to preload SDRAM is for bonus points really, as it would give me a way to preload much larger "disc" content. But I'm actually wondering how practical this might be, due to the need for continual refresh. {{{ Andy

Hi Andy, The way a processor normally deals with this boot-strapping issue is; 1) The processor has a memory map. The memory map can contain; on-board RAM/ROM, external Flash, SRAM, SDRAM, etc. 2) When the processor boots, it fetches its first instructions from the reset vector. In your case, the reset vector could be located in on-chip ROM or off-chip flash. 3) The power-on or bootloader, or crt0.s (c runtime setup), code then sets up the system. On a microcontroller, this might mean setting up PLLs and peripherals, but with an FPGA, these can be designed to power-up in sane states. For you, its mainly setting up the processor registers, and relocating code from Flash to SRAM/SDRAM. Your processor would copy code and data from Flash over to on-board SRAM, or external SRAM or external SDRAM. Once the code is copied over, the boot code can setup the stack pointer (if your 8-bit micro has one), and then jump into your 'main' application. Your micro's code will have a linker map telling it where to place read-only variables, read/write variables and data. You compiler will generate assembly instructions with relative offsets referencing the addresses in those locations. This is how the code looks after you have copied it from flash. --- Quote Start --- As the flash has 70ns access time, I may need to add wait states to the CPU --- Quote End --- The processor core most definitely needs some way to force wait-states (unless you plan on running it at a few kHz clock rate). The simplest system for you to design would be to create a wrapper to convert the processor into an Avalon-MM master. Then you can drop it into an SOPC or Qsys System. I know, it looks like a daunting amount of information to absorb, but the benefit is that you get the Flash, SRAM, and DDR controllers provided to you. You can also drop a NIOS or OpenRISC processor into your system and check that it works. That'll help in debugging. --- Quote Start --- Being able to preload SDRAM is for bonus points really, as it would give me a way to preload much larger "disc" content. But I'm actually wondering how practical this might be, due to the need for continual refresh. --- Quote End --- Refreshing the DDR is the job of the DDR controller, not your CPU. So, as long as you use a provided DDR controller, you don't have to think about it (once you've figured out how to get it working). Cheers, Dave

Hey Andy, http://www.nyangau.org/rememotech/rememotech.htm I don't see any mention of Modelsim here. If you really want to make sure things work, then I'd recommend getting a simulation of your core working under Modelsim first. Don't even bother trying to debug in hardware until you can boot your processor under Modelsim. Something as simple as a toggling I/O pin would be a major milestone. From there, it should be trivial to get it working in hardware. In fact, its only an 8-bit micro, so it can almost certainly be designed to boot from an on-chip RAM. Cheers, Dave

Yes, I totally get the whole overview 2 posts above. But I have no plan to use SOPC or Avalon, partly because I don't want to be tied to them, and partly because there are implementations out there I can model on that don't pre-req any or all of that. If I had been designing a new system from scratch, for a real commercial purpose, then perhaps I'd be more inclined to use these tools, which seem to be step up a level in productivity. My problem is as was originally stated, how to pre-load various forms of memory on the DE1 card, as simply as possible, given my current tooling. Once, its in there, given the pre-existing success of others, I think my design should work fine. Yes, I may need some wait state logic if I am to use Flash, but the Z80 (and thus T80) should support that fine. I do appreciate that ModelSim etc are important. Although its an 8-bit micro, the ROM+RAM requirements are non-trivial in terms of size. So although I could put a small boot ROM into M4K, and although that could copy from Flash to SRAM, I would still need a lot of content initially loaded to Flash. The SDRAM controller thought I had was this: The mechanism to load SDRAM might involve a special .pof downloaded to the FPGA (isn't that how Control Panel works?), and this could include refresh logic. But then I'd need to download my real .pof, also with refresh, and I'm wondering how long the SDRAM lasts before losing content, in the period in which the new .pof is being programmed into the FPGA. Anyway, this aspect is less important. {{{ Andy

Loading SRAM,SDRAM or FLASH on DE1, using Linux, without Qsys, SOPC or NIOS

19 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

SignalTap in particular looks promising.

--- Quote End ---
Here's a quick getting started guide for you.

1) Bring up the SignalTap GUI.

2) Click on the setup tab (you'll see it near the bottom left, its probably selected by default).

3) Double click in the blank area. This will bring up the Node Finder GUI.

4) On the 'Filter:' menu, select 'SignalTap II: pre-synthesis'. Then click on the list button.

5) Double click on signals in the list on the left side of the GUI to add them to your signaltap signal list (they appear on the right). When you're done, click ok.

6) Select a sampling clock. On the right side of the GUI click on the button next to the clock source. It brings up the Node Finder GUI again. Select pre-synthesis again, and then select a clock source, eg., clkin_50MHz (or whatever your external clock is called).

7) Select a sample capture depth, eg., 2k (its on the right, under the clock selection)

8) Save the SignalTap setup (click yes when it asks you if it should add the setup to the current design), and resynthesize your design.

9) Download the new design and SignalTap should detect it (if not, on the right hand side of the Signaltap GUI, select the USB-Blaster and scan for the design).

Have fun!

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Have set up SignalTap.
However, the jtag side of it seems unreliable, at least for me.
After downloading a new .pof, I need to stop Quartus, kill jtagd, start up Quartus, and then start SignalTap.
This kinda breaks the edit, compile, debug cycle, which is not nice.
If I don't do this, when I click on "Run Analysis" the "Status" reports as "Invalid data received".
If I then click on "Read Data" data does come back, and it looks kinda believable, but it can be very misleading, because it doesn't know where the sample begins and ends - the end of the sample can be to the left of the start of the sample.
This caused me to (incorrectly) think my program counter had magically jumped backwards for no reason!

As I'm on 64 bit Fedora 14, to get Quartus working at all, I needed to put symlinks in for missing libraries, some of which support running jtagd - so my problems could be related to that.
Having Quartus (including jtagd and SignalTap) work out of the box on more Linux flavours would be nice.

I also get 10 lines of warnings when the USB blaster stuff is loaded at boot time like this:
udevd[470]: BUS= will be removed in a future udev version, please use SUBSYSTEM= to match the event device, or SUBSYSTEMS= to match a parent device, in /etc/udev/rules.d/51-usbblaster.rules:8

All in all, a great tool - shame about the jtagd problems.

{{{ Andy
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Have set up SignalTap.
However, the jtag side of it seems unreliable, at least for me.

--- Quote End ---

Yeah, I've noticed a few annoying things too.

For example, if working with system-console, I need to make sure I close any JTAG connections before starting signal tap (the GUI), and then open a JTAG connection in system-console before starting signaltap acquire.

Once I figured out the sequence that works, then its been ok.

--- Quote Start ---

I'm on 64 bit Fedora 14

--- Quote End ---

I have been doing my development under WinXP and Win7. I have got Quartus installed under VirtualBox + Ubuntu and Centos 6.2. Though I haven't played much with signaltap, so I don't know if the same sequence is required.

--- Quote Start ---

Having Quartus (including jtagd and SignalTap) work out of the box on more Linux flavours would be nice.

--- Quote End ---

From Altera's perspective, I'm sure they're thinking "Having less flavors of Linux to choose from would be nice ... " :)

--- Quote Start ---

I also get 10 lines of warnings when the USB blaster stuff is loaded at boot time like this:
udevd[470]: BUS= will be removed in a future udev version, please use SUBSYSTEM= to match the event device, or SUBSYSTEMS= to match a parent device, in /etc/udev/rules.d/51-usbblaster.rules:8

All in all, a great tool - shame about the jtagd problems.

--- Quote End ---

I haven't noticed those errors ... I'll have to keep an eye out for them.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
FYI, problem solved now.
Flash mapped into CPU memory space.
SPI interface to SD card constructed and mapped into CPU IO space.
Tiny on-chip ROM contains code to read SD and write flash.
Really not that hard to do in the end.
SPI is really quite straightforward, thanks to Wikipedia article and sample code on an Arduino site.

{{{ Andy
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
FYI, problem solved now.
Flash mapped into CPU memory space.
SPI interface to SD card constructed and mapped into CPU IO space.
Tiny on-chip ROM contains code to read SD and write flash.
Really not that hard to do in the end.
SPI is really quite straightforward, thanks to Wikipedia article and sample code on an Arduino site.

--- Quote End ---

So your Z80 processor boots now? Cool! :)

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Actually its been booting and been doing lots of stuff for quite a while.
For example, driving (testing) the text mode video adapter I built.
The T80, combined with z80soc, gives a good model to start from.
Its just until now, all the code had to fit in on-chip (FPGA M4K or LE) memory.
In my design, I will eventually have >=72KB of ROM, which is too much to do this way.

{{{ Andy
Altera_Forum
Honored Contributor
13 years ago
Guys,

I have some doubts.
I'm building a system based on another one that I have (DE2_NET - it is in DE2 CD ROM), so I'm trying to understand what the function of each memory element.

We find these in the project (one of each):

Avalon MM Tristate Bridge
Flash Memory
EPCS Serial Flash Controller
SDRAM

The Resect_vector is pointing to Flash Memory and the exception_vector to SDRAM.

My doubts:

I think that the the .elf is being downloaded to the flash memory, I'm correct?
1. What's the function of each one?
2. Why I need to use EPCS?
3. I only can use flash memory whe I'm using a Avalon MM Tristate Bridge?

Ps.: I'm reding some documentations but the differences are still not clear.

Thanks
Altera_Forum
Honored Contributor
13 years ago
Flash memory is probably a parallel memory chip while the EPCS is a serial configuration device for the FPGA. Both are able to contain the .elf file. Do you really have both memories on the board? Do you intend to use one for the FPGA configuration and another one for the software?
With the EPCS there is a bootloader in the controller that copies the .elf contents to main RAM and runs the application there. With a parallel flash you have the choice between using a bootloader that would also copy the application to main memory, or execute the software directly from the flash.
Altera_Forum
Honored Contributor
13 years ago
Thanks, now I understand!

The flash memory is a paralel memory. I won't use the EPCS serial configuration.
I'm storing the .elf into the flash and the library provides to me a software to copy the code and run over SDRAM.

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Loading SRAM,SDRAM or FLASH on DE1, using Linux, without Qsys, SOPC or NIOS

19 Replies

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