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Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
4 years ago

llegal connection on I/O input buffer primitive [1704]

Hi, I have this issue with net that drives out to destinations other than the specified I/O.

i saw it also on the EMIF DDR3 Intel sample design i generated ..

it happened when instantiation in the TOP during synthesis and analysis.

the OCT logic cant drive the I/O buffer for impedance calibration .

tried 8 OCT bus vs signal but that did not help too.

no signal tap in the design . below the error . what can be the cause for that ?

do you know solution ?

Error(17044): Illegal connection on I/O input buffer primitive sys|emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.ibuf. Source I/O pin sys|emif_c10_0|emif_c10_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

7 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Avichay,


    Can you please elaborate what you are trying to achieve when you say "net that drives out to destinations other than the specified I/O"?


    A pad pin of the FPGA is hardwired to an input buffer. It cannot drive the internal FPGA core logic directly. So make sure that you are not inserting any logic in between the pad and the buffer.

    To enable OCT for differential pins, you can enable it in the Pin planner or in the .qsf file.


    Regards.


    • Avichay's avatar
      Avichay
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi Ash_R

      Thanks for answering.

      pls see attached screen shot of the issue.

      the qsys of the example design ed_synth works ok but when putting it on a simple top i get the below error.

      The error i get is :

      Error(17044): Illegal connection on I/O input buffer primitive u0|pci_ddr_emif_0|pci_ddr_emif_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.ibuf. Source I/O pin .

      Thanks,

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Are the inputs to the buffer, io and iobar connected as ports at the top entity, ecb.vhd?


    • Avichay's avatar
      Avichay
      Icon for New Contributor rankNew Contributor
      4 years ago

      no , you are right , one of them was not connected on top.

      It now does analysis ok.

      One pin in the top was not defined .

      The error message is 'complicated' but solution is simple.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Glad to know that the issue is resolved. Closing this case. Thanks for contacting!!


    Regards.


  • j130198's avatar
    j130198
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi,

    I'm facing the same issue and haven't been able to find a solution yet. I tried the suggested solution, but I'm afraid I didn't fully understand it. Could someone provide me with more guidance, or perhaps a step-by-step tutorial? I would greatly appreciate any help you can offer. Thank you!