Forum Discussion

Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
4 years ago

llegal connection on I/O input buffer primitive [1704]

Hi, I have this issue with net that drives out to destinations other than the specified I/O. i saw it also on the EMIF DDR3 Intel sample design i generated .. it happened when instantiation in th...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Avichay,


Can you please elaborate what you are trying to achieve when you say "net that drives out to destinations other than the specified I/O"?


A pad pin of the FPGA is hardwired to an input buffer. It cannot drive the internal FPGA core logic directly. So make sure that you are not inserting any logic in between the pad and the buffer.

To enable OCT for differential pins, you can enable it in the Pin planner or in the .qsf file.


Regards.


Avichay's avatar
Avichay
Icon for New Contributor rankNew Contributor
4 years ago

Hi Ash_R

Thanks for answering.

pls see attached screen shot of the issue.

the qsys of the example design ed_synth works ok but when putting it on a simple top i get the below error.

The error i get is :

Error(17044): Illegal connection on I/O input buffer primitive u0|pci_ddr_emif_0|pci_ddr_emif_0|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.ibuf. Source I/O pin .

Thanks,