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Honored Contributor
Honored ContributorLinking of two FPGA
Hi all, I'm a student of Engineering of Telecommunications.In my thesys I must realize a digital circuit on FPGA,but I can't make it all on the same FPGA board,because of occupation of resources.S...
Altera_ForumHonored Contributor
Honored ContributorOn your previous post, a Tco of 35.6 seems really long, but you should be using static timing analysis(TAN or TimeQuest) to analyze it further, not just the info message. If it's an old process or there's a lot of logic, it's certainly possible.
Timing inside a device is considerably different than externally. The drive strength of the internal transistors, the capacitive loading, etc. all make a difference. I wouldn't try comparing the two.
