limited timing information for Arria II GX

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we are developing an interface board for signal conversion. The incoming signal is sampled at 1.2 GHz (parallel input 14 bit). Two output channels are

planned to work at 150 MHz maximum. Arria II GX (EP2AGX65DF29C4) seemed to be the right choice using differential LVDS inputs.

But we cannot perform a verification simulation. Quartus II reports:

"Error: Quartus II software currently does not support the generation of timing analysis netlists for Arria II GX device family"

Since our time frame is rather limited, we need quickly a solution that works:

- is there an alternative for Arria II GX which is fully supported ?

- are there other sources to get detailed timing information for our netlist from ?

- how would you suggest to proceed further ?

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I'm not sure that you need to use the Arria II GX devices. Do you really need the transceivers? The LVDS on the Stratix II devices operate at up to 1Gbps, and with DPA they are supposed to operate at up to 1.6Gbps.

I've used the LVDS at up to 1Gbps to interface to e2v's 8-bit 1GHz ADCs. Test data is here:

http://www.ovro.caltech.edu/~dwh/carma_board/index.html

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf

Cheers,

Dave

We have updated to Quartus 10.0SP1 (Linux version) before testing.

Regards,

Mine_Lamp

According to the 11.0 SP1 Device Support Release notes, the Arria II GX family timing sshould have been final in 10.0SP1.

However Arria II GZ wasn't final until 10.1. I would move to 11.0SP1 however for the best device support. I have heard there was several issues with 10.0.. I don't know if they were all fixed in SP1 or not.

Pardon ! I have caused confusion:

We have installed the most recent version of Quartus last week, so it is 11.0SP1 (mistyping at late hour). To us this message seems to be crucial for our Arria II project. Right ?

Do we need to use special definitions for the LVDS-inputs in Quartus ? Like superblocks etc.? We did not find any hints in documentation. Is the treatment of LDVS inputs similar for Stratix II or completely different ? Does it make sense to set up a Quartus project for

Stratix II in parallel in order to select the FPGA-family later on ?

Up to now the board design is not finished. We require a valid verification simulation before finally specifying the input and output pins on board level.

Thanks for yor support

Mine_Lamp

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Do we need to use special definitions for the LVDS-inputs in Quartus? Like superblocks etc.?

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To use I/O pins with LVDS logic levels, you simply need an I/O constraint. However, for reception of Gbps data, you will need to use an LVDS SERDES, or a transceiver channel (available only on GX devices). The two megafunctions are altlvds and altgx.

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We did not find any hints in documentation. Is the treatment of LDVS inputs similar for Stratix II or completely different?

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Read the digitizer tests document I posted. It shows you the interface requirements for LVDS. LVDS can be configured synchronously, so you will have no problems receiving data. The transceiver serdes lanes are essentially independent, with independent clock recovery, unless your ADC is JEDEC JESD204A/B/C compatible, or has a PRBS generator for lane alignment, you will need to do a lot of work to interface to it.

What is the part number you are trying to interface to?

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Does it make sense to set up a Quartus project for

Stratix II in parallel in order to select the FPGA-family later on ?

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Setup a Modelsim simulation to get the interface working, and then a Quartus project to check that timing can be met.

Cheers,

Dave