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Altera_Forum's avatar
Altera_Forum
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14 years ago

limited timing information for Arria II GX

Hello, we are developing an interface board for signal conversion. The incoming signal is sampled at 1.2 GHz (parallel input 14 bit). Two output channels are planned to work at 150 MHz maximu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Pardon ! I have caused confusion:

We have installed the most recent version of Quartus last week, so it is 11.0SP1 (mistyping at late hour). To us this message seems to be crucial for our Arria II project. Right ?

Do we need to use special definitions for the LVDS-inputs in Quartus ? Like superblocks etc.? We did not find any hints in documentation. Is the treatment of LDVS inputs similar for Stratix II or completely different ? Does it make sense to set up a Quartus project for

Stratix II in parallel in order to select the FPGA-family later on ?

Up to now the board design is not finished. We require a valid verification simulation before finally specifying the input and output pins on board level.

Thanks for yor support

Mine_Lamp