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Do we need to use special definitions for the LVDS-inputs in Quartus? Like superblocks etc.?
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To use I/O pins with LVDS logic levels, you simply need an I/O constraint. However, for reception of Gbps data, you will need to use an LVDS SERDES, or a transceiver channel (available only on GX devices). The two megafunctions are altlvds and altgx.
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We did not find any hints in documentation. Is the treatment of LDVS inputs similar for Stratix II or completely different?
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Read the digitizer tests document I posted. It shows you the interface requirements for LVDS. LVDS can be configured synchronously, so you will have no problems receiving data. The transceiver serdes lanes are essentially independent, with independent clock recovery, unless your ADC is JEDEC JESD204A/B/C compatible, or has a PRBS generator for lane alignment, you will need to do a lot of work to interface to it.
What is the part number you are trying to interface to?
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Does it make sense to set up a Quartus project for
Stratix II in parallel in order to select the FPGA-family later on ?
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Setup a Modelsim simulation to get the interface working, and then a Quartus project to check that timing can be met.
Cheers,
Dave
Honored Contributor
