Limited clock freq on altremote_update iface?

I'm doing an A2GX design that includes an altremote_update block to an EPCS218 device. My altremote_update module is fed from a 100MHz clock that the other logic on the board uses. TimeQuest is reporting a failed constraint on this clock, indicating the max clock speed of this block is 10MHz.

I've used this block before on an S2 design, and it had no problems running the interface at 100MHz and connected directly to a Nios processor. I don't see anything in any documentation about a 10MHz limit on the A2gx.

Has anyone else experienced this?

Quartus II 9.1 SP2

Win7 64-bit

EP2AGX45

TimeQuest reports:

Info: Node : remote_upd:inst3|remote_upd_rmtupdt_5ol:remote_upd_rmtupdt_5ol_component|wire_sd1_regout

Info: Clock : inst|bup_nios_instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[1] (INVERTED)

Info: Type : Min Period

Info: Required Width : 100.000

Info: Actual Width : 10.000

Info: Slack : -90.000 (VIOLATED)