Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

lightweight bridge address for DE1-SoC board

Hi there! I try to do some exercises with Terasic's DE1-Soc Cyclone V board. As a first exercise I'm trying to send data from the HPS to the FPGA over the lw bridge, using the FPGA as an Avalon...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It's part of the HPS specs. I typically refer to this when I'm trying to figure out the memory map: http://www.altera.com/literature/hb/cyclone-v/hps.html (that bridge is "lwfpgaslaves"). When you connect the lightweight H2F bridge to soft logic in the FPGA, the physical address of the soft IP is 0xFF20_0000 + base address of soft IP.