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Honored Contributor
Honored ContributorLFSR as counter in VHDL
I am running a bit low on gates in a VHDL design, and I am replacing a counter implemented by addition with a counter implemented as an LFSR. The main crystal is 3.6864 MHz and the counter needs to h...
Altera_ForumHonored Contributor
Honored ContributorFlexible counters are easy to design and for small counters there is no noticeable advantage in speed and logic size comparing to LFSR counters. I agree, you can use memory to implement larger counters. However, memory output delay might be too large to meet timing.
Also, it's less portable if your design has to run on different FPGA and ASIC families. - Evgeni
