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Honored Contributor
Honored ContributorLFSR as counter in VHDL
I am running a bit low on gates in a VHDL design, and I am replacing a counter implemented by addition with a counter implemented as an LFSR. The main crystal is 3.6864 MHz and the counter needs to h...
Altera_ForumHonored Contributor
Honored ContributorBen - thank you; that either worked properly, or it generated a sequence long enough that it doesn't matter. Perhaps someday I will even understand why.
You're right about mirror sequences; looks like, for tap sequence [n,A,0] there is a mirror at [n,n-A,0]; I guess n=20, A=3 here.
