Large delay between DMA transactions

Dear All,

We are utilizing HPS-side DMAC controller and very similar results measured as in case of the -jaro's comment (as saying "built-in DMA").

My question is why the buffer size is limited in 2 MB when alt_dma_zero_to_memory / alt_dma_memory_to_memory / alt_dma_reg_to_memory API functions are used?

Symptom: if the buffer size is increased above 2 MB then an alt_dma_event_int_status_get_raw() never returns with ALT_E_SUCCESS.

Neither Cyclone V SoC device handbook, nor ARM's CoreLink DMA 330 Controller technical ref. guide (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/ddi0424d_dma330_r1p2_trm.pdf) mention about this limitation.

However this latter guide is useful if you want to modify the microcode program of DMAC controller.

Thanks

Zsolt