Large delay between DMA transactions

Hi Jaro, for# 1 at the end of your post you are correct you need to handle the valid signal for the write path and the ready signal in read path. These signals are well documented in the Avalon-ST spec and shorting them together may work in your case but in general data only moves into the write master or out of the read master when valid and ready are both high. When you short them together you loose the ability to provide flow control so if you see redundant/missing samples then that's why because you lost your back-pressure mechanism by shorting them together.

By the way if you want to hide read latency between MM-->ST or MM-->MM transfers using the mSGDMA enable the 'early done enable' bit (24) in the control field of the descriptor. This makes sure that the read master starts working on the next descriptor before all the read data returns from memory.