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Hello ,
Thank you for reply.
Probably you are right about possible reasons .
I have added "alt_cache_system_enable(); //cache enable "
function to the init procedure , but without success ( no influence at the large delay).
The question is still open : how we can improve the built-in DMA ?
At this moment I'm testing different properties of the SoC System , and my test
programs are very simple , i.e code to test buit-in DMA is like below (main section) :
int main(int argc, char** argv)
{
system_init(); //init: gpio , bridge , dma , timer , cache enable
soc_int_setup(); //setup interrupt
global_timer_init(); //start timer (i.e. 10 ms interval)
uart0_init(); //start uart
generate_test_data(); //generate Write_Buffer[]
while (1)
{
if (GLOBAL_TIMER_SEMAPHORE==true) //triggered every 10 ms interval
{
GLOBAL_TIMER_SEMAPHORE=false;
for (int i=0 ; i<128 ; i++) // try to call i.e 128 DMA transactions (every transaction has got the
length 128 32-bits word)
{
LED_GPIO_State^= 0x10000000;
alt_gpio_port_data_write(ALT_GPIO_PORTA, 0x10000000, LED_GPIO_State); // LED
//
// here is a large delay between LED and the time when DMA data are visible (about 50 us)
//
//call DMA , DMA transfer time is about. 3.3 us (approx. 307 MBytes/s)
dma_test_memory_to_register( &Write_Buffer[0], (uint32_t *)(ALT_LWFPGA_BASE +
ALT_LWFPGA_LED_OFFSET) , 128);
//
// small delay (approx. 4.1 us) to the time when "ALT_DMA_CHANNEL_STATE_STOPPED " is returned
//
}
} //timer
} //while
return 0;
} //main
My questions :
1) Is it possible to change something in the code or DMA init to remove delays ?
2) Now I'm trying to implement mSGDMA on the FPGA and compare the built-in DMA and
the mSGDMA. I have a lot of troubles with connecting mSGDMA to the HPS system
( not to the Nios !!! ) . Does anybody know how to do it ( especially how to write
driver code for bare-metal aplication ) ?
Regards
-jaro
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I've successfully implemented the mSGDMA controler. It's quite simple if you know how to do it
http://www.alteraforum.com/forum//images/icons/icon7.png If you need DMA to transfer data between FPGA --> HPS SDRAM or HPS SDRAM --> FPGA
the mSGDMA module is much better than built-in DMA controler.
System description:
1) mSGDMA module connected to F2S ( FPGA --> SDRAM bridge) , not to the F2H AXI.
2) mSGDMA setup: Memory -> Stream or Stream -> Memory
Data width = 64 bits
Data FIFO Depth =64
Desc FIFO Depth =64
Transfer Length = 1kB or 16 kB
Burst enable , Max. Burst Count = 16
Measurements result:
mSGDMA Transfer Length = 1kByte :
1024 packets * 1kB , Memory -> Stream , Throughput = approx. 290 MBytes/s (good !!!)
1024 packets * 1kB , Stream -> Memory , Throughput = approx. 290 MBytes/s (good !!!)
mSGDMA Transfer Length = 16kByte :
64 packets * 16kB , Memory -> Stream , Throughput = approx. 378 MBytes/s (good !!!)
64 packets * 16kB , Stream -> Memory , Throughput = approx. 378 MBytes/s (good !!!)
For built-in DMA I've got following results :
1 packet of 1 MBytes , Memory -> Memory , Throughput = approx. 423 MBytes/s ( very good !!!)
1 packet of 1 MBytes , Memory -> Register , Throughput = approx. 38.4 MBytes/s ( poor !!!)
1024 packets of 1kByte , Memory -> Memory , Throughput = approx. 16.1 MBytes/s ( very poor !!!)
1024 packets of 1kByte , Memory -> Register , Throughput = approx. 11.7 MBytes/s ( very poor !!!)
The last results due to large delay between consecutive DMA transactions !!!!
Important notices about mSGDMA and F2S implementation ( poorly documented) :
1) you must to service the signals :msgdma_valid and msgdma_ready on the FPGA side
(i.e. connect these signals together !!!!)
2) you must to define ALT_BRIDGE_PROVISION_F2S_SUPPORT =1 in your Makefile (read in HWLib help)
3) you must to link assembly file like this : alt_bridge_f2s_gnu.s in your Makefile (read in HWLib help)
4) you must to initialize F2S bridge in your program !!!!
i.e. alt_bridge_init (ALT_BRIDGE_F2S, NULL , NULL)
Regards
-jaro
Honored Contributor
