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The reason is likely because a lot of error checking and validation goes into building each of the DMA programs. Things such as the following:
- validating that program buffer have enough space to contain the entire requested program
- register and memory addresses are aligned
- all loops well-formed
- program is well formed
- program is synced to RAM
- (list goes on).
Things you can do to improve performance are as follows:
- Setup the MMU page table and enable all caching (for 14.0, if you are using a flat VM model, it will work correctly. What I call flat is when all virtual addresses matches with the physical addresses).
- You can try hand editing out the error checking but I don't know how much gains it will get you.
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Hello ,
Thank you for reply.
Probably you are right about possible reasons .
I have added "alt_cache_system_enable(); //cache enable "
function to the init procedure , but without success ( no influence at the large delay).
The question is still open : how we can improve the built-in DMA ?
At this moment I'm testing different properties of the SoC System , and my test
programs are very simple , i.e code to test buit-in DMA is like below (main section) :
int main(int argc, char** argv)
{
system_init(); //init: gpio , bridge , dma , timer , cache enable
soc_int_setup(); //setup interrupt
global_timer_init(); //start timer (i.e. 10 ms interval)
uart0_init(); //start uart
generate_test_data(); //generate Write_Buffer[]
while (1)
{
if (GLOBAL_TIMER_SEMAPHORE==true) //triggered every 10 ms interval
{
GLOBAL_TIMER_SEMAPHORE=false;
for (int i=0 ; i<128 ; i++) // try to call i.e 128 DMA transactions (every transaction has got the
length 128 32-bits word)
{
LED_GPIO_State^= 0x10000000;
alt_gpio_port_data_write(ALT_GPIO_PORTA, 0x10000000, LED_GPIO_State); // LED
//
// here is a large delay between LED and the time when DMA data are visible (about 50 us)
//
//call DMA , DMA transfer time is about. 3.3 us (approx. 307 MBytes/s)
dma_test_memory_to_register( &Write_Buffer[0], (uint32_t *)(ALT_LWFPGA_BASE +
ALT_LWFPGA_LED_OFFSET) , 128);
//
// small delay (approx. 4.1 us) to the time when "ALT_DMA_CHANNEL_STATE_STOPPED " is returned
//
}
} //timer
} //while
return 0;
} //main
My questions :
1) Is it possible to change something in the code or DMA init to remove delays ?
2) Now I'm trying to implement mSGDMA on the FPGA and compare the built-in DMA and
the mSGDMA. I have a lot of troubles with connecting mSGDMA to the HPS system
( not to the Nios !!! ) . Does anybody know how to do it ( especially how to write
driver code for bare-metal aplication ) ?
Regards
-jaro
Honored Contributor
