Large delay between DMA transactions

The reason is likely because a lot of error checking and validation goes into building each of the DMA programs. Things such as the following:

- validating that program buffer have enough space to contain the entire requested program

- register and memory addresses are aligned

- all loops well-formed

- program is well formed

- program is synced to RAM

- (list goes on).

Things you can do to improve performance are as follows:

- Setup the MMU page table and enable all caching (for 14.0, if you are using a flat VM model, it will work correctly. What I call flat is when all virtual addresses matches with the physical addresses).

- You can try hand editing out the error checking but I don't know how much gains it will get you.