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Altera_Forum's avatar
Altera_Forum
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15 years ago

Lack of write to LUT or small ram in Altera

As far as I can tell, Altera LUT ram does not allow writing by user logic.

This prevents a small ram from being implemented. My understanding

is that Xilinx has patents ( expired ? ) on distributed rams. But surely

just having a write to a LUT does not infringe on any patents.

So why does Altera not allow user logic to write a LUT ?

Anyone has a better insight ?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for the info. I'll be looking forward to Cyclone 5. Small lut rams can

    be very useful & an advantage compared to asic designs. I am converting

    a Xilinx design into Altera & found the lack of small rams hindering. But then I figured out a different design which does away with the small rams

    entirely. Lucky this time but I'll certainly look forward to Altera lut rams.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Cyclone III/IV? That's correct, although the devices have smaller RAMs meant for this purpose. Stratix IV and all future families do allow the LAB to be converted to a small RAM, so it is there on the high end and coming on the less expensive FPGAs.

    (Note that there is a silicon expense in hardware for doing this. I belive both X and A only allow it on every other column or something like that because of that...)