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Altera_Forum
Honored Contributor
Honored ContributorLack of write to LUT or small ram in Altera
As far as I can tell, Altera LUT ram does not allow writing by user logic. This prevents a small ram from being implemented. My understanding is that Xilinx has patents ( expired ? ) on distrib...
Altera_ForumHonored Contributor
Honored ContributorCyclone III/IV? That's correct, although the devices have smaller RAMs meant for this purpose. Stratix IV and all future families do allow the LAB to be converted to a small RAM, so it is there on the high end and coming on the less expensive FPGAs.
(Note that there is a silicon expense in hardware for doing this. I belive both X and A only allow it on every other column or something like that because of that...)
