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ManthanWankar's avatar
ManthanWankar
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3 years ago

Kernel restart issue while trying to read or write from the address space of hps2fpga and lwhps2fpga

Currently working on a Arria 10 FPGA and faced this issue while trying to access the gpio connected on the lwhps to fpga bridge but when i try to access the lwhps2fpgs address section(0xff200000) my kernel stucks and restarts.

below i have mentioned the bridge device tree

fpga-bridge@ff200000 {
compatible = “altr,socfpga-lwhps2fpga-bridge”;
reg = <0xff200000 0x00200000>;
resets = <0x06 0x61>;
clocks = <0x08>;
bridge-enable = <0x01>;
altr,l3-syscon = <0x99>;
phandle = <0x5b>;
init_val = <1>;

};

fpga-bridge@c0000000 {
compatible = “altr,socfpga-hps2fpga-bridge”;
reg = <0xc0000000 0x3c000000>;
resets = <0x06 0x60>;
clocks = <0x08>;
bridge-enable = <0x01>;
altr,l3-syscon = <0x99>;
phandle = <0x5c>;
init_val = <1>;
};
been following this guide from rocket board: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
and also can any one please share the correct device tree for fpga2hps and fpgs2sdram bridge device tree node

Configuration

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  • ManthanWankar's avatar
    ManthanWankar
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    3 years ago

    this is the GSRD qsys and i have added some FPGA led to it

  • ManthanWankar's avatar
    ManthanWankar
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    3 years ago

    what are your device tree defination for the l3 register look like.

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi ManthanWankar,


    I was able to execute bridge enable in Uboot user space using GSRD build and can detect the same sys id from the System ID Peripheral Intel FPGA IP which connected to 0xFF200000.

    If I didnt perform bridge enable, the system will reset/restart after I execute md 0xFF200000 in Uboot user space.


    May I know which device tree file which you change for uboot referring to the link below:

    https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2023.01

    Is it possible to compare/test with GSRD before any changes being made?



    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi ManthanWankar,


    Is there any error return when execute bridge enable?

    If there is no error then when peform md 0xff200000, the system will reset?

    Are you using the GSRD from building bootloader to test before any modification?

    I can try to test the GSRD on my side but will need some time to do that.


    Thanks.

    Regards,

    Aik Eu




    • ManthanWankar's avatar
      ManthanWankar
      Icon for New Contributor rankNew Contributor
      3 years ago

      no error returned while bridge enable

      yes it will give a data abort error and the system will reset.

      yes i am using the GSRD only have changed the memory size from 1GB to 2GB else every thing is the same

      the default device tree does not have fpga bridges in it's device tree node so have added those.

      • ManthanWankar's avatar
        ManthanWankar
        Icon for New Contributor rankNew Contributor
        3 years ago

        also using quartus pro 22.4 instead of quartus pro 23.2

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi ManthanWankar,


    Can you try to perform bridge enable in Uboot user space before booting into linux kernel?


    Thanks.

    Regards,

    Aik Eu


    • ManthanWankar's avatar
      ManthanWankar
      Icon for New Contributor rankNew Contributor
      3 years ago

      have tried that too, also tried to access the registers from uboot , got data abort error.

      the bridges are enable i can see the state of bridge in /sys/class/fpga_bridge/br*/state as enabled