Occasional Contributor
Regular ContributorWhenever I have had a requirement to do this I just add an external passive pulldown/pullup resistor, as appropriate, of a value that holds the signal level to a correct value when the FPGA is unconfigured/unpowered, and can be overridden by an actively driven output.
I have never had an issue using this approach.
Occasional ContributorYes, that is what I want, so I filled in actual resistor values that would fit these criteria (in a worst-case scenario), and I'm rather unhappy with how far away the signal levels are from the supply rails, how little tolerance I have for the resistor values and how much drive current I need in the FPGA -- so I'm wondering if I've overlooked something.
I get much better values for normal operation if I calculate with the typical rather than minimum resistance of the internal pull-up, but if in series production I happen to get an FPGA with a stronger pull-up, I end up with a board that will activate the FET during the configuration phase, which is not the safe state of the machine as a whole, so I wouldn't sign off on that as production ready.
Regular ContributorThe CycloneV electrical datasheet (version 2016.06.10) lists the pullup value as 25Kohm +/- 10% over PVT (note 17 on page).
