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Altera_Forum
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9 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
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Altera_Forum
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8 years ago

Hello Anand,

On my second board, I tried the SOF first and it programmed without any issue, on the first attempt itself.

On trying the POF file, I got the following message..

Info (209060): Started Programmer operation at Wed Dec 06 17:04:27 2017

Info (209017): Device 1 contains JTAG ID code 0x031820DD

Info (209044): Erasing MAX 10 configuration device(s)

Info (209023): Programming device(s)

Info (209021): Performing verification on device(s)

Error (209048): Verify failure on device number 1

Error (209012): operation failed (83% on the 'Progress' bar)

Info (209061): Ended Programmer operation at Wed Dec 06 17:07:13 2017

On trying again, I get following message right away, as before...

Info (209061): Ended Programmer operation at Wed Dec 06 17:07:13 2017

Info (209060): Started Programmer operation at Wed Dec 06 17:07:51 2017

Info (209017): Device 1 contains JTAG ID code 0x031820DD

Info (209044): Erasing MAX 10 configuration device(s)

Warning (16328): The real-time ISP option for Max 10 is selected. Ensure all Max 10 devices being programmed are in user mode when requesting this programming option

Error (209012): operation failed