JTAG timing constraints

OP (with the Arria V) reporting in.

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I wonder if there's been any further progress or a 'definite conclusion' on this matter?

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I made a separate support ticket for this issue; Altera's response can be summarized as follows:

• Not the whole JTAG controller is hard IP, therefore timing constraints are vital.

• This is are the currently recommended constraints: https://www.altera.com/support/support-resources/knowledge-base/tools/2016/why-do-i-see-jtag-problems-when-using-the-signaltap-ii-logic-ana.html

• There are no known Arria V issues related to our issue.

Our strategy is to try out these new constraints on future designs. We haven't gotten around to testing them on the affected design. Thus no progress or definite conclusion from our side.