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Altera_Forum
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8 years ago

JTAG timing constraints

Hi, Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria ...
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Altera_Forum
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8 years ago

Hi

1.Is JTAGEN pin of MAXa0 device handled same in both the boards?

2.Is nSTATUS CONF_DONE nCONFIG pulled up with 10K?

3.Is TDI and TMS pulled up?

4.What is the status on CONF_DONE pin when nSTATUS is low?

5.If you schematic followed all the guidelines. there should not be a problem and trace length difference will also not affect the signal properties at lower frequency so even that's fine(length difference can be 100mil to 200mil generally)

6.Do you get message during configuration can you attach screen short of it.(put it in word and attach as word file)

Or

Can you write simple program (control led using switch) and load the file and check.(To recheck the programming steps)

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)