JTAG Header for HPS and FPGA

Hi Joe,

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Hello, I would like to use one JTAG header for the FPGA side and one header for the HPS side of the side will this be a problem? I thought this would make this less complex. My co-worker daisy-chained the JTAG with the FPGA being first in the chain and then the HPS. I've looked at the documentation but haven't found an example of using a separate header. Can anyone help?

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I think you probably want to have two separate connectors, but not for the reason you state.

ARM processor JTAG interfaces include the JTAG signals and a number of other trace signals. If you look at the Altera Cyclone SoC Development kit schematic (contained within the ES .zip file installation) you'll see that the board has a Mictor connector for the HPS JTAG and trace signals, and then a USB-Blaster connector on another page. I do not have this board, so have not read the details on the two JTAG interfaces. I recommend you take a look at it.

Research the connectors used by commercial ARM debuggers and see if they come with the Mictor connector, or some other adapter, I recall a 20-pin adapter being used by some ARM processors.

Cheers,

Dave

Dave,

Hi, thank you for responding to my post. I am new to the ARM processor so please excuse my questions. My first one is, "to debug the HPS does it require a special programmer that has a Mictor connector?" Also, when you are bebugging the system it would then appear that you need both programmers connected one for the HPS and one for the FPGA. Is the software able to debug both HPS and FPGA at the same time, I thought that would be done through a single JTAG connection. I have been looking over the SX Cyclone Deve Kit (5CSXFC6D6F31C8NES) and I do see that they are using a Mictor Connector so I will have to do some more reading on this connector. Although it is a little difficult to see the JTAG flow for the FPGA and the HPS because of the switches.

If you do use a single JTAG for the HPS and FPGA are there any limitations? I ask because that is what my co-worker did and his board is now in PCB layout.

Thanks again,

joe

Hi Joe,

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My first one is, "to debug the HPS does it require a special programmer that has a Mictor connector?"

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I have not used the HPS devices so cannot comment. I have used other ARM-based processors and their JTAG features vary depending on whether they support full-trace, JTAG, or SWD. So basically there are many options, so you need to investigate which option will work best with the Cyclone SoC.

I can guarantee that debugging will be "easier" if you have full trace support, so try to make sure you include it on your prototype version of your hardware. You can always not populate when you get to production.

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Also, when you are bebugging the system it would then appear that you need both programmers connected one for the HPS and one for the FPGA.

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That would depend on the software being used to debug. The HPS has a scan manager that can take over the FPGA JTAG. That implies that it should be possible to use the HPS JTAG interface to debug both the core and the FPGA fabric. However, just because the FPGA supports this does not mean the debugger software does, so you'll have to do some more reading :)

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Is the software able to debug both HPS and FPGA at the same time, I thought that would be done through a single JTAG connection. I have been looking over the SX Cyclone Deve Kit (5CSXFC6D6F31C8NES) and I do see that they are using a Mictor Connector so I will have to do some more reading on this connector. Although it is a little difficult to see the JTAG flow for the FPGA and the HPS because of the switches.

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I do not have an HPS board, so cannot comment. Hopefully others will chime in with their experience.

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If you do use a single JTAG for the HPS and FPGA are there any limitations? I ask because that is what my co-worker did and his board is now in PCB layout.

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I'm sure it will work fine. You just won't be able to use the hardware trace pins.

Personally I would design the JTAG interface to support both the Mictor and the standard USB-Blaster header and add multiplexing logic to support either one of these connectors, or both operating independently. I suspect the SoC kit multiplexing allows something like that. Read the SoC kit documentation and see if they describe the JTAG chain.

Cheers,

Dave