Forum Discussion
IAbid
New Contributor
New Contributorjtag Daisy Chain compiler setting ?
Hi, I need some information regarding a design, where if two devices are JTAG daisy chained e.g. Altera CPLD and Atmel SAM4E series microcontroller. As far as the hardware and layout is concerned, ...
Nooraini_Y_Intel
Frequent Contributor
Frequent ContributorHi IAbid,
Happy New Year. Please refer to the attached document for the steps to add and bypass non-Intel (Altera) FPGA/CPLD devices in Quartus programmer tools. Thank you.
Regards.
Nooraini
