Forum Discussion

New Contributor

7 years ago

jtag Daisy Chain compiler setting ?

Hi, I need some information regarding a design, where if two devices are JTAG daisy chained e.g. Altera CPLD and Atmel SAM4E series microcontroller. As far as the hardware and layout is concerned, ...

Nooraini_Y_Intel

Frequent Contributor

7 years ago

Hi IAbid,

Happy New Year. Please refer to the attached document for the steps to add and bypass non-Intel (Altera) FPGA/CPLD devices in Quartus programmer tools. Thank you.

Regards.

Nooraini

How to add non-Altera devices into the Quartus programmer .docx1.1 MB

Forum Discussion

jtag Daisy Chain compiler setting ?

Recent Discussions

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information

Cyclone 10 LP's Extended Industrial parts