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Basically, the initially chain identification just does this: sending a recognizable pattern. But as you already stated, it's unaware of logic delays, only counting a register length. To compensate for a register delay, two prerequisites have to be met:
- the JTAG TCK timing must be fully under your control, which is possible with e.g. an embedded JAM player but would be a problem with Quartus JTAG tools
- the JTAG SERDES must use an synchronous clock and oversample the input data. Practically, a CPLD with a byte parallel interface to your embedded JTAG software could perform this task.
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Thanks for the reply. We will be using an embedded JAM player -- probably implemented in an FPGA, so the TCK timing is under control. The SERDES clock is synchronous with the TCK,
and on the return, the SERDES uses the clock recovered from the downlink deserializer.
The only thing that is missing is the revised code to support it -- I had hoped not to have to reinvent the wheel if it had already been done. :rolleyes:
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