Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorJTAG configuration over fiber link
We are deploying a Cyclone III FPGA in a remote location, connected to the infrastructure by a 30m long duplex optical fiber pair. TDI, TCK, TMS are sent to the remote FPGA, TDO comes back on the ret...
Altera_ForumHonored Contributor
Honored ContributorBasically, the initially chain identification just does this: sending a recognizable pattern. But as you already stated, it's unaware of logic delays, only counting a register length. To compensate for a register delay, two prerequisites have to be met:
- the JTAG TCK timing must be fully under your control, which is possible with e.g. an embedded JAM player but would be a problem with Quartus JTAG tools - the JTAG SERDES must use an synchronous clock and oversample the input data. Practically, a CPLD with a byte parallel interface to your embedded JTAG software could perform this task.
