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Yes. JTAG is designed to work up to 0.5 clock cycle delay. Could be possibly extended to 1 cycle by adding a register that's clocked on the other edge, but not more.
To compensate for a multiple clock cycle delay, a synchronous design with a fixed clock frequency is needed, but it's sensitive to delay skew. A clear solution would be to send a Rx clock back with TDO.
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Unfortunately, there are no free bits in the return direction on the (serialized) payload.
I know what needs to be done: a recognizable TDI pattern has to be sent [once] which allows the software to calculate the number of clocks before the pattern appears on the return line.
Once that is known, this delay can be inserted before any attempt to deal with the returning TDO bitstream following any TDI input.
I had hoped that someone might have already done this ...
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