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Honored Contributor
Honored ContributorJTAG configuration over fiber link
We are deploying a Cyclone III FPGA in a remote location, connected to the infrastructure by a 30m long duplex optical fiber pair. TDI, TCK, TMS are sent to the remote FPGA, TDO comes back on the ret...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The distribution manages to figure out how many devices are on the chain, but not how much external delay there is.. --- Quote End --- Yes. JTAG is designed to work up to 0.5 clock cycle delay. Could be possibly extended to 1 cycle by adding a register that's clocked on the other edge, but not more. To compensate for a multiple clock cycle delay, a synchronous design with a fixed clock frequency is needed, but it's sensitive to delay skew. A clear solution would be to send a Rx clock back with TDO.
