jtag configuration by external processor

Can I ask why you are trying to configure the FPGA via JTAG from your processor rather than using the slave serial/parallel options that are intended for this purpose? Is this an academic exercise or this a real application on real hardware?

The JTAG spec is not something Altera have put together, it's a standard supported by Altera devices. See: 1149.1-2013 - ieee standard for test access port and boundary-scan architecture (http://standards.ieee.org/findstds/standard/1149.1-2013.html)

Cheers,

Alex

--- Quote Start ---

so anyone can tell to where to find the REAL working spec about the altera FPGA's JTAG programming?

--- Quote End ---

Unfortunately one does not exist. There are "hints" of the JTAG instructions and programming sequence in the JRunner software package, but nothing official.

Xilinx has done a much better job of specifying their programming protocols and providing tools.

As Alex points out, the "recommended" programming method for Altera FPGAs via a processor are the passive serial (PS) and fast passive parallel (FPP) modes, or you can use SPI to program an SPI flash, and then allow the FPGA to boot from that flash.

If you have no choice but to use JTAG (due to hardware limitations), then take a look at the JRunner software

https://www.altera.com/download/legacy/jrunner/dnl-jrunner.html

Cheers,

Dave

you are right, ps is a better choice

i want to use jtag just because i read out the jtag id by openocd very easy. and openocd support some X-device directly,so i thought maybe A-device can be support by openocd too...

--- Quote Start ---

i want to use jtag just because i read out the jtag id by openocd very easy. and openocd support some X-device directly,so i thought maybe A-device can be support by openocd too...

--- Quote End ---

You're fighting several battles here; the USB-Blaster protocol is not officially published, but it has been reverse-engineered, and that allows OpenOCD to use the USB-Blaster as a JTAG probe.

The JTAG protocol defines some standard instructions, of which the IDCODE is a standard instruction, so OpenOCD can read the FPGA ID code. Unfortunately the instructions associated with programming a device via JTAG are not published, so it is not possible for OpenOCD to support device programming.

Altera have added an FPGA manager to their new SoC devices. That FPGA manager allows you to "take over" the FPGA JTAG and program the device. I have not investigated the software associated with that feature, but you may find that it exposes the programming instructions (at least those used on the newer generation devices).

Cheers,

Dave

--- Quote Start ---

I am still working on it. does anyone make a progress ?

--- Quote End ---

Still working on which aspect?

Cheers,

Dave

--- Quote Start ---

working on the JTAG instruction for JTAG configuration

--- Quote End ---

Which FPGA?

Did you take a look at the JRunner code.

https://www.altera.com/download/legacy/jrunner/dnl-jrunner.html

It should be fairly simply to trace the JTAG traffic, or to add debug statements to that code to determine the JTAG instructions.

The JRunner software has hooks for you to integrate your own custom I/O functions. If I wanted to know the JTAG instructions, I would re-write the I/O procedures such that the I/O toggles also controlled a software-based JTAG TAP machine, and then have that software log the instructions and data to file.

Cheers,

Dave