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Altera_Forum
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14 years ago

JTAG chain debugger tools scripts & JTAG clock management

Hi everyone, For a design tests, I'm planning to implement this design to a Cyclone II FPGA (integrated to a DE1 board). I then would like to apply stimuli on DUT inputs via the JTAG chain an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello,

Thank you for the information, it can be a useful feature.

However I'm not using any Avalon bus as my system validates different modules which will be integrated to an ASIC.

Thank you for your answer and do not hesitate to share some answers to my questions or any other clues...

Regards,

J-B