JTAG and AS configuration on Cyclone IV

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I would like to understand if I can only use the AS connector in my circuit, and in this case,

can I leave the lines TDI TDO TMS and TCK free?

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It's possible to omit JTAG interface, but you can neither use JTAG debug functions nor boundary scan for in circuit test then. Why not implement JTAG only and program AS flash through JTAG using jic method?

Hi Clros,

You can refer to the similar thread below.

https://alteraforum.com/forum/showthread.php?t=46140

jic method - Configuration file that enables indirect programming of a FPGA devices through a

JTAG (Joint Test Action Group) used by Quartus Tool.

For Interface circuit between JTAG and memory, refer to the link below.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf - Page 19 & 55

https://www.altera.com/documentation/mwh1410805299012.html

Refer to the Cyclone IV Design Guidelines link below for more information,

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an592.pdf

Yes you can capture a board with only AS programming. However, I wouldn't. JTAG can prove very useful.

I agree with FvM - this is what I do regularly. Only connect up JTAG and program your configuration device via the FPGA using a .jic file (JTAG Indirect Configuration).

Refer to an 370: using the intel fpga serial flash loader with the intel quartus prime software (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an370.pdf) which discusses this in detail.

Cheers,

Alex