New ContributorボードにはCPLD(MAXII.)、FPGA(サイクロンV)およびCFIフラッシュメモリがあります。
(FPGA構成はFPP x16)CPLDは(パラレルフラッシュローダ)PFLで設計されています。 プログラマ(20.1)を使用して、JTAGでCPLD(MAXII.)にpofを書き込み、再び自動検出する場合異常(申し訳ありません!メッセージ(申し訳ありません!表示され、プログラマーを終了するしかありません。 (***
致命的なエラー: 0X00007FFB3C5E2B2E) でのアクセス違反)
異常の原因を教えてください。
また、CPLDを一度消去する方法を教えてください。
Regular ContributorHi,
Could you provide the full fatal error message log file?
New ContributorThis is the error message log.(Jtag_fail_log.txt)
Regular ContributorHi,
It looks like it might be related to your system OS memory crash when as the Quartus is running multi threading. May I know if this is happening on single system or multiple system?
Is it easy to duplicate the issue?
New ContributorIt occurs in multiple systems (3 PCs).
It's easy to reproduce the problem
・Programmer (17.0) does not generate Fatal Error It may be.
・Programmer (20.1) gives 100% Fatal Error.
Regular ContributorMay I know what is the 3 PC specification?
New Contributor1.Intel(R) Core i7-3370 CPU , RAM 8GB, OS Windows10 Pro (2004)
2.Intel(R) Core i7-3370 CPU , RAM 16GB, OS Windows10 Pro (2004)
3Intel(R) Core i7-6700k CPU , RAM 64GB, OS Windows10 Pro (2004)
Regular ContributorHi,
Can you try using the latest Quartus 20.4 to see if the issue is still observed?
New ContributorQuartus Prime Standard Edition latest 20.1.1
(Device used FPGA Cyclone V)
Download and try Quartus Prime Pro Edition Programmer and Tools 20.4
New ContributorThere was a mistake in the pin assignment between the CPLD and CFI Flash connection.
Correcting the CPLD pin assignment no longer causes a Fatal Error.
Thank you for everything.
Regular ContributorI am glad he issue is fixed after fixing the pin assignment
New ContributorCPLD pin assignment error is the cause of JTAG Fail Error Is there a way around the JTAG Fail Error?
