New Contributor
New ContributorSince I don't have time, I will share other test results with you.
In the above IP (JESD204C) settings, we changed and tested many things.
We also checked many CSR Registers, and changed and tested many of them. (Actually, there were not many things that could be set.)
The FPGA part of our board is as follows:(JESD204C RX)
RFIC side(JESD204C TX)
When operating an FPGA with the corresponding IP applied, JESD RX Capture is as follows.
The timing of each LOCK that occurs at this time is as follows. (491.52M cpature base)
The order of occurrence is correct, but I don't know if the exact timing is correct (not in the document). Is that correct?(CRC_error is occurring.)
Status Register (0x60)
CDR LOCK/crc_error occurs
It was deleted, but only CDR_unlock was deleted.
The incoming data is as follows.
If normal, the signal should be All Zero.
In case of RFIC, in case of RF_RX OFF, all zero is transmitted when JESD link is alive.
csr_reinit timing(JESD RX only)
The LOCK sequence occurs the same as at the initial link_up (exact timing cannot be confirmed).: Right???
LANE Status:
Why LANE 0/1??? Isn't it LANE12 or 13?
CDR Lock Status:
CDR/SH/EMB LOCK
Polarity Inversion
IP Parameter Setting = 0x00000000, But set status = 0x00000003
Are all of these LSB <<-- MSB problems?
RFIC Company talks about RBD optimization.
Intel says that RBD optimization is automatic for the IP.
Do I need to manually optimize again?
There's a lot of content, it's hard work, but please respond.
