JESD204B Multi-Link configuration with Different Link Parameters on Stratix10

Hi all,

I am working on a project using an FPGA Stratix 10 GX Transceiver-based Development Kit.I have shared below the parameters and configuration details used in my setup.

Hardware Configuration:

FPGA: Stratix 10 GX Transceiver-based Development Kit

ADC Devices: 3 × AD9695

Active Channels: 5 complex DDC outputs

Interface: JESD204B Subclass 1

RX Lanes: 10 total

Data Format: Complex I + Q from DDCs

JESD204B IP Core Settings:

Link 1 (ADC1): M = 8, L = 4, S = 1 → (JESD204B IP Core, Link = 1)

Link 2 (ADC2): M = 8, L = 4, S = 1 → (JESD204B IP Core, Link = 2)

Link 3 (ADC3): M = 4, L = 2, S = 1 → (JESD204B IP Core, Link = 3)

According to Intel Application Note 804, the multi-link JESD204B example design supports configurations only when all links have identical parameters.In my case, the third ADC (Link 3) uses different JESD204B parameters (M and L values) compared to the first two ADCs.

I would like to know:

Can multiple JESD204B RX IP cores with different link parameters be used in the same design?If yes, how should I structure the Platform Designer system and clocking hierarchy?If not, what is the recommended Intel design flow or alternative approach to integrate multiple ADCs with different JESD parameters on the Stratix 10 platform?

Additional Details:

All ADCs share a common SYSREF generated from an LMK device.

Lane rate: 8.192 Gbps

JESD204B subclass: Subclass 1

Please guide me on how to proceed with this configuration whether to use multiple JESD204B IP instances, modify the multi-link example, or apply any Intel-recommended method for mixed link parameter setups.

Thanks