Issues using IOWR for SPI communications

I have updated - it seems that the CACHE is not getting updated. But another unfortunate findings was that the functions to update cache (alt_dcache_flush_all()) are excluded from our library - so I cannot use them. I tried the below code and it worked:

Refer Doc - https://www.intel.com/content/www/us/en/docs/programmable/683282/current/cache-considerations-for-writing-program.html

/*
* Assume new instruction in r4 and
* instruction address already in r5.
*/
stw r4, 0(r5)
flushd 0(r5)
flushi r5
flushp

Hence in below C code I implemented below assembly instruction code to achieve it:

.... C code ....

__asm__ ("movi r3,0x80");
__asm__ ("movi r2,0x8c");
__asm__ ("stw r3,0x0(r2)");
__asm__ volatile("flushd 0x0(r2)");

.... C code ....

The above code worked though should I be using below code:

__asm__ ("movi r3,0x80");
__asm__ ("movi r2,0x8c");
__asm__ ("stw r3,0x0(r2)");
__asm__ ("flushd 0x0(r2)");
__asm__ ("flushi r2");
__asm__("flushp");

My question now is can we directly use r2 and r3 registers as above. Which of the above two code sections I can use? Should we not get the value of them and restore back after the flushd assembly instruction - if so please let me know how in a C program I can achieve this?

Also should we always make use r2 and r3 register? Can we use any register as used above?

What would be the best code to implement in C code otherwise?