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PrakashPrasad's avatar
PrakashPrasad
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2 years ago
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Issues using IOWR for SPI communications

I am having difficulty using the IOWR and IORD functions in NIOS II.

We have a ENUM like below:

#define BASE 0x80

typedef enum SPI_REGISTERS_tag
{
READ_REG_5_E = 0x00,
WRITE_REG_0_E = 0x01,
SPI_STATUS_WORD = 0x02,
SPI_CONTROL_WORD = 0x03

} SPI_REGISTERS;

For SPI communication to send data we need to write 0x80 at I/O address 0x8C

When we use the below statement it works fine:

*(U32*)0x8C = 0x80;

But with below code the objective is not met:

IOWR(BASE, SPI_CONTROL_WORD, 0x80);

Which translates to below code:

__builtin_stwio (((void *)(((alt_u8*)(0x80)) + (((SPI_CONTROL_WORD)) * (32/8)))), (0x80));

When I read back the value written using above statement for address 8C I get value 0x10?

We tried to use IOWR32_DRIECT() but still the same issue. We verified the assembly instruction and they differend in stw / stwio instruction note that we are using data cache:

*(U32*)0x8C = 0x80;
00C02304 movi r3,0x8C ; r3,140
00802004 movi r2,0x80 ; r2,128
18800015 stw r2,0x0(r3) ; r2,0(r3)

IOWR(BASE, SPI_CONTROL_WORD, 0x80);
18800035 stwio r2,0x0(r3) ; r2,0(r3)


I also tried making the CACHE size to 0 but no success.

What wrong am I doing and fix required to achieve the objective?

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    2 years ago

    Hi,

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


    Thank you.

    Regards,

    Kelly Jialin, GOH


12 Replies

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


    Thank you.

    Regards,

    Kelly Jialin, GOH


  • PrakashPrasad's avatar
    PrakashPrasad
    Icon for New Contributor rankNew Contributor
    2 years ago

    I have updated - it seems that the CACHE is not getting updated. But another unfortunate findings was that the functions to update cache (alt_dcache_flush_all()) are excluded from our library - so I cannot use them. I tried the below code and it worked:

    Refer Doc - https://www.intel.com/content/www/us/en/docs/programmable/683282/current/cache-considerations-for-writing-program.html

    /*
    * Assume new instruction in r4 and
    * instruction address already in r5.
    */
    stw r4, 0(r5)
    flushd 0(r5)
    flushi r5
    flushp

    Hence in below C code I implemented below assembly instruction code to achieve it:

    .... C code ....

    __asm__ ("movi r3,0x80");
    __asm__ ("movi r2,0x8c");
    __asm__ ("stw r3,0x0(r2)");
    __asm__ volatile("flushd 0x0(r2)");

    .... C code ....

    The above code worked though should I be using below code:

    __asm__ ("movi r3,0x80");
    __asm__ ("movi r2,0x8c");
    __asm__ ("stw r3,0x0(r2)");
    __asm__ ("flushd 0x0(r2)");
    __asm__ ("flushi r2");
    __asm__("flushp");

    My question now is can we directly use r2 and r3 registers as above. Which of the above two code sections I can use? Should we not get the value of them and restore back after the flushd assembly instruction - if so please let me know how in a C program I can achieve this?

    Also should we always make use r2 and r3 register? Can we use any register as used above?

    What would be the best code to implement in C code otherwise?

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Greetings and welcome to Intel's forum.

    May I know if you have include the header file <sys/alt_cache.h> so that the function alt_dcache_flush_all() can be called?


    Hope to hear on your response.


    Thank you.

    Regards,

    Kelly Jialin, GOH



    • PrakashPrasad's avatar
      PrakashPrasad
      Icon for New Contributor rankNew Contributor
      2 years ago

      Thanks for the update - I added the header file and the alt_dcache_flush_all() API call in my code but during compilation I get error like:-

      undefined reference to `alt_dcache_flush_all'

      Do we need to add any specific library for same to resolve?

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    One more thing to check is that after adding in your .h header file, is the c code file present ? As the error message indicates that the c code file is missing and not added.


    Looking forward to hearing from you.


    Thank you.


    Regards,

    Kelly


  • PrakashPrasad's avatar
    PrakashPrasad
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thanks for valid information - unfortunately it seems that our code base build did not include the required .c files.

    Hence I am only left with the assembly instruction way - please let me know if there is any alternative mechanism if any

    Thanks in advance

  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,

    Any updates from your end from your end? Is the feedback provided useful? You may check the SPI base offset address whether it is correct.


    Thank you.


    Regards,

    Kelly


  • PrakashPrasad's avatar
    PrakashPrasad
    Icon for New Contributor rankNew Contributor
    2 years ago

    The issue turned out that we needed to flush the CACHE. I do not have the underlying code but flushing the value worked for me.

    Thanks for all your help