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mwf's avatar
mwf
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3 years ago

Issue with updating ARIA 10 PCIe core to 20_1_1

We are migrating to a new hardware design server and are converting existing FPGA designs from Quartus 17.1 to Quartus 22.3. We have a number of PCIe Gen 3 x 8 designs that build without issue and ru...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I wish to follow up with you about this case. Any update after rebuild ?

Regards,

Wincent_Intel


mwf's avatar
mwf
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3 years ago

Hi Wincent. I did another scrub of the differences between the designs, specifically the .qsf and source files. Nothing stood out. I then compared the .sdc files and found a flase path constraint in the Gen 2 x 8 design that was not present in the Gen 3 x 8 design. Once I removed the constraint, which was a bit heavy handed, the design runs fine on the hardware.

Thanks for your assistance,

Mike

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    Glad that the problem is solved, thanks for sharing the answer with me.

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel