New Contributor
Regular ContributorHi,
Sorry for late reply due to holiday session
I check internal information, for Arria 10 we do not suggest direct migration from gen2x8 to gen3.
I will raise an internal ticket for this, hope the related team will work on this in next release version of update (but I cannot promise that)
I lay down some of the suggestion.
Regards,
Wincent_Intel
New Contributor1. We are not migrating a design from Gen 2 x8 to Gen 3 x 8. By the way that works fine but is not part of this discussion. I can move freely from Gen 2 x 8 with a 125 mhz 256 bit internal bus to a Gen 3 x 8 with a 250 mhz 256 bit bus. That is not the issue here. This issue is when we migrated a Gen 2 x 8 design from Quartus 17.1 to Quartus 22.3 it stopped compiling correctly. A Gen 3 x 8 design migrated from 17.1 to 22.2 works fine.
2. That could be an option but what is the point in using 6 year old software on a design that has a production part on it.
3. Sigh, that is what this entire thread is about. We recomplied a design in the newest version of Quartus and it stopped compiling reliably.
Regular ContributorHi,
My fault did not check correctly before sent out the mail.
What I mean was direct migration from Quartus v17.1 to any newer version instead of direct migration from gen2x8 to gen3.
Can you share with me the .qar file ? I can try to compile on my place and see if I able to run full compilation or not.
Regards,
Wincent_Intel
New ContributorHi Wincent. We already have sent a qar file via our distributor Arrow and Intel was able to compile it successfully.
The issue is not the compile but the compilation result not working.
Here is some more information that may be useful.
This is a working PCIe status:
Failing, you can see the latency is 0xff and the Max Payload is different.
Above is the most serious error. As I mentioned some builds work, some have the above issue, and others hang the PC when I try to do DMA to the host.
This shows there is something fundamentally wrong with the build.
Thanks,
Mike
