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Altera_Forum
Honored Contributor
Honored ContributorIs this already maximally pipelined ... anything I can do to speed this up?
According to .sta.rpt Fmax for this is 307 MHz which is less than 50% of the datasheet listed max speed... wbr Kusti
always @(posedge sys_clk) begin
if (($signed({1'd0, e}) | (count...
Altera_ForumHonored Contributor
Honored ContributorIn the assignments editor, one of the options is "virtual_pins". Assign this to *. This means it will not connect the interface of your design to any pins. It is only for testing resource usage and fmax estimates. Dont use it in final builds.
