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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is this already maximally pipelined ... anything I can do to speed this up?

According to .sta.rpt Fmax for this is 307 MHz which is less than 50% of the datasheet listed max speed... wbr Kusti always @(posedge sys_clk) begin if (($signed({1'd0, e}) | (count...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi, thanks for answering.

The code is generated by Migen which (I guess) just in case adds those signed stuff there. Anyways, this is not real production code as such, just experimenting to get some guidelines for speed as to which way to go.

Ok, thanks for confirming that this cannot be much improved. The chip is Arria 10 (mid speed, don't could not rely related the speed class of the chip with the data sheets speed).

Yes, this was top level test, how should I set the pins virtual, this is not clear to me?

thanks again, Kusti