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3 Replies
- Altera_Forum
Honored Contributor
Please explain better what you need.
If you simply want to connect a 7 segment display to a binary counter, here is some VHDL code.
I don't describe connection between SEG bits and each display segments, since it should be easy to understand. Crisentity decoder7seg is port (DIGIT : in std_logic_vector(3 downto 0); SEG : out std_logic_vector(6 downto 0) ); end entity decoder7seg; architecture decoder7seg_a of decoder7seg is begin --decode : process DIGIT is SEG <= "0111111" when DIGIT="00000" else -- 0 "0000110" when DIGIT="0001" else -- 1 "1011011" when DIGIT="0010" else -- 2 "1001111" when DIGIT="0011" else -- 3 "1100110" when DIGIT="0100" else -- 4 "1101101" when DIGIT="0101" else -- 5 "1111101" when DIGIT="0110" else -- 6 "0000111" when DIGIT="0111" else -- 7 "1111111" when DIGIT="1000" else -- 8 "1101111" when DIGIT="1001" else -- 9 "1110111" when DIGIT="1010" else -- A "1111100" when DIGIT="1011" else -- b "0111001" when DIGIT="1100" else -- C "1011110" when DIGIT="1101" else -- d "1111001" when DIGIT="1110" else -- E "1110001" when DIGIT="1111" else -- F "0000000"; end architecture decoder7seg_a; - Altera_Forum
Honored Contributor
SEG <= "0111111" when DIGIT="00000" else -- 0
i think it should be DIGIT="0000" ... - Altera_Forum
Honored Contributor
That's right.
This is because my original code had a 5bit DIGIT input in order to display extra 7seg characters. I modified the code on the fly in order to reduce to standard 4bit decoder but I forgot that line. Sorry for the mistake. Regards