New ContributorHi, I am using 10ax115R3F40
Question 1: I cant found VCCP and VCCa_pll pins on my sch lib downing from intel website. Do it say that these two type pin no need connect? But it have VCCa_fpll. Is this mean vcca_fpll instead vcca_pll?
Question 2 : I dont use Tranceivers. But I use IOPLL. Can i connect vcch_gxbl/vcch_gxbr/vcct_gxbl/vcct_gxbr to GND?
Thank you!
Frequent ContributorHi Niko
Can you share with us the link where you downloaded those Arria 10 files?
For Arria 10 pin connection, we shall always refer to pin connection guideline:
https://www.intel.com/content/www/us/en/programmable/documentation/wtw1404286459773.html
Thanks.
Eng Wei
New ContributorHello wei
I download the orcad sch lib from https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html
Frequent ContributorHi Niko
While I am still having issue opening the .OLB file, let me put my comment as follow.
For 1st Question, referring to the pin list below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-10/10ax115.pdf
and pin connection guideline below:
https://www.intel.com/content/www/us/en/programmable/documentation/wtw1404286459773.html
VCCP and VCCA_pll need to be connected
For 2nd question, referring to pin connection guideline above:
"If all of the transceivers, fPLLs, and IOPLLs on a side are not used, then the VCCT_GXB power rails on that side can be tied to GND to save power regardless of whether they are an inner or outer bank."
"VCCH_GXBR power rails can be tied to GND to save power if all of the transceivers, fPLLs, and IOPLLs on that side are not used."
Since you are using the IOPLL, you need to connect those pins.
Thanks.
Eng Wei
