Is there a standard way to store and retrieve "build information" of an FPGA design?

Hi,

You have to execute the qsys-generate in the command line terminal instead of the TCL Console in the Intel Quartus Prime software.

You may specify the language when you execute this command. Attached is the help for your reference

Thanks.

Hi,

May I know if you have any updates?

Thanks.

I wrote a custom tcl script that generates a VHDL file with the compilation data and time, and the git hash values. This package is included into a register bank in the design. The register bank already exists and stores many different type of data used by the design. The register bank code is all in VHDL.

The compilation data and time, and the git hash values for the repositories that form the project can be read by using system console.

​The project is now being compiled using a script based flow. It shall generate the Qsys system before synthesis. I did include the .qsys file into the design so Quartus automatically generates the Qsys system. However, I noticed that it (automatically) generates verilog synthesis files rather than VHDL files. It is not clear how to specify Quartus to automatically generate VHDL synthesis files instead when .qsys file is included into the project.

Hi,

You may go to Assignments > Settings > IP Generation HDL preference, set to VHDL

Thanks.

Hi,

Do you have any updates?

Thanks.