Is there a standard way to store and retrieve "build information" of an FPGA design?

Hi,

You may execute the TCL script (let say first.tcl) that is use to update the HDL file of the custom Qsys component before synthesis by adding the command in the .qsf.

set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:first.tcl

For further information, you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-scripting.pdf (Chapter 1.9 Automating Script Execution)

You can either add the qsys-generate command in the first.tcl and add the above command in the .qsf file

or

create a .tcl that list all the execution flow in sequence and run the tcl.

Please let me know if you have any questions.