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gyuunyuu's avatar
gyuunyuu
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6 years ago

Is there a standard way to store and retrieve "build information" of an FPGA design?

The following things are to be stored inside the FPGA: 1. Build date 2. Build time 3. Build top level file name 4. Build repository commit number for version controlled design 5. Submodule repos...
gyuunyuu's avatar
gyuunyuu
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6 years ago

OK, I will ask an alternate question. I have tcl script that can execute and generate those values into a HDL file just before synthesis takes place. I just want ​to know what command has to be run from tcl to cause the Qsys system to generate again. If I am using shell , I can use the "qsys-generate".

What if I want to update the HDL file of a custom Qsys component via a tcl script, just before synthesis and then cause the Qsys system to regenerate just before synthesis starts? The "qsys-generate" can be run from shell but what do I need to use from the tcl script?