Forum Discussion
Honored ContributorIs SystemVerilog Catching on for Design
Hello, I'd like to know how how popular SystemVerilog is today, how many people are switching from Verilog to SV? I'm pretty much a AHDL guy but I've been trying to teach myself Verilog. One thing that bothers me is that I can find lots of books on Verilog for design but most books on SystemVerilog are for Verification or Testbenches. I thought it would be better to learn Verilog and try it out on a few designs and then try to learn SystemVerilog.
If anyone has some comments to share please do. Also if you have any good web sites on learning SV or Verilog please share them too. Thanks, joe15 Replies
Altera_Forumhi guys,
actually SystemVerilog is not an HDL language for designing and synthesizing a circuit. it "adds" some system-level features to a lower-level language like verilog, which is good for describing a system or performing verification of the designs. in contrast, a language like SystemC adds a lower-level features to higher-level language (C++) to accomplish the same thing. adel- Altera_Forum
Hi guys, well i started directly on Verilog, and i have been doing it for 4 years now, i am also curious about SV, what will it really do for my designs?
as far as i could see its a change to a more C-like structure of coding, but will it actually improve the code itself? - Altera_Forum
If you are to use HDL language I recommand SystemVerilog. Learn verilog first then jump all in to system verilog. You just have more with SystemVerilog.
Here is a book about SystemVerilog for design. It's not a great book,but it will do for now systemverilog for design second edition: a guide to using systemverilog for hardware design and modeling (hardcover) by stuart sutherland, simon davidmann, peter flake, and p. moorby (hardcover - jul 20, 2006) make sure you get the second edition - Altera_Forum
Gregg,
Hello, thanks for the link and the encouragement. joe306 - Altera_Forum
Hi Joe -
I'm a former AHDL guy, now Verilog guy. I just started learning SystemVerilog a couple weeks ago. It is very much 'Verilog with some add-ons' rather than a new beast. The addons are GREAT if you find yourself wanting C-like structures / datatypes. There are some nice new features for doing constrained random simulation, and asserts. A couple of minor annoyances in the Verilog syntax are removed. I started off with this link from some language buffs. It's a little bit out of date, but it sums up the Verilog / SV changes pretty well. http://www.sutherland-hdl.com/papers/2003-systemverilog_white_paper.pdf The SV support in Modelsim and Quartus is pretty good. You can tell it isn't quite as polished as the straight Verilog, but pretty civilized. -Gregg
