Is SystemVerilog Catching on for Design

Hi Joe -

I'm a former AHDL guy, now Verilog guy. I just started learning SystemVerilog a couple weeks ago. It is very much 'Verilog with some add-ons' rather than a new beast. The addons are GREAT if you find yourself wanting C-like structures / datatypes. There are some nice new features for doing constrained random simulation, and asserts. A couple of minor annoyances in the Verilog syntax are removed.

I started off with this link from some language buffs. It's a little bit out of date, but it sums up the Verilog / SV changes pretty well.

http://www.sutherland-hdl.com/papers/2003-systemverilog_white_paper.pdf

The SV support in Modelsim and Quartus is pretty good. You can tell it isn't quite as polished as the straight Verilog, but pretty civilized.

-Gregg