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Honored Contributor
Honored ContributorIs SystemVerilog Catching on for Design
Hello, I'd like to know how how popular SystemVerilog is today, how many people are switching from Verilog to SV? I'm pretty much a AHDL guy but I've been trying to teach myself Verilog. One thing th...
Altera_ForumHonored Contributor
Honored ContributorHi Joe -
I'm a former AHDL guy, now Verilog guy. I just started learning SystemVerilog a couple weeks ago. It is very much 'Verilog with some add-ons' rather than a new beast. The addons are GREAT if you find yourself wanting C-like structures / datatypes. There are some nice new features for doing constrained random simulation, and asserts. A couple of minor annoyances in the Verilog syntax are removed. I started off with this link from some language buffs. It's a little bit out of date, but it sums up the Verilog / SV changes pretty well. http://www.sutherland-hdl.com/papers/2003-systemverilog_white_paper.pdf The SV support in Modelsim and Quartus is pretty good. You can tell it isn't quite as polished as the straight Verilog, but pretty civilized. -Gregg
